Our client’s creative and talented team is disrupting the way SoCs are designed. You will play a key role in driving IP system architectures for clocking and timing IP and systems. You may lead improvements and new feature development in application-optimized IP across multiple products.

DUTIES INVOLVED BUT NO LIMITED TO:

  • System modeling of complex timing IP such as digital PLLs
  • Interpretation and analysis of silicon results and diagnostics
  • Apply new concepts in timing and clocking circuits
  • Develop innovative new features both customer-driven and internally designed

YOU ARE:

  • You have an MS or Ph.D. in EE or ECE & at least 3+ years of experience in relevant feedback control systems
  • Excellent understanding of noise, jitter and other timing phenomena
  • Familiar with SERDES, PLL or other high-performance systems where CDR, DFE and other DSP techniques may be required
  • You should also have hands-on experience with the following tools
    • Matlab or equivalent
    • Verilog
    • Python (scripting)
    • C/C+

Interested:

Send us your resume and cover letter describing your suitability to [email protected] for this dynamic position. Thank you for your submission, but only those selected for an interview will be contacted. SearchForce is an equal opportunity employer/agency, regardless of race, color, creed/religion, sex, sexual orientation, marital status, age, mental or physical disability.

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